Four-core AMD Opteron for the server market by 2007

The server version of this chip will add a third level of cache memory to AMD's processors, allowing server designers to build systems with 16 and 32 processors, Hester said. Previously AMD's customers had been limited to building eight-processor Opteron servers because of the difficulty inherent in coordinating cache memory requests within multiprocessor servers. Cache memory stores frequently used data on the chip close to the CPU, where it can be accessed much more quickly than data stored in memory.

The third level of cache memory will allow 32-processor Opteron servers without the need for external logic to coordinate the cache memory on those processors. AMD partner Newisys introduced a chipset on Monday that can support 32-processor servers, but it requires special logic that won't be necessary with the 2007 processor, Hester said.

But before this new Opterons ship on 2007, new dual-core Opterons will be released in 2006 with some relatively modest changes like support for DDR2 memory and a new socket technology that uses a different pin structure than the sockets currently used on most Opteron and Athlon 64 processors. The 2006 Opterons will introduce AMD's Pacifica virtualization technology and its Presidio security technology into AMD-based systems. Pacifica improves the performance of virtualization hardware with dedicated transistors, and Presidio creates a protected area of the processor for storing critical data.

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